1. Field of the Invention
The present invention relates to a method for fabricating a flat cell memory device and, more particularly, to a method of fabricating a silicide layer of flat cell memory device capable of lowering electric resistance of interconnection line in a highly-integrated design rule by forming a silicide layer on a word line of flat cell region except for active region of the flat cell region and forming a salicide layer on a word line and active region of peripheral circuit region.
2. Description of the Related Art
Generally, a mask ROM is a nonvolatile device for storing information using a mask process in a device fabrication process. Even though the mask process for storing information can be performed in an isolation process or metal wiring process, it is generally performed by implanting ions into channel regions of memory cell. In this case, the ion-implanted cell has a different threshold voltage from that of non ion-implanted cell, thereby reading stored information. Generally, ROMs including the mask ROM have a flat cell structure to improve operation speed by increasing cell current.
FIG. 1 is a layout of mask ROM having a common flat cell structure, wherein a plurality of BN+ (Buried N+ channel) diffusion layers 18 are arranged with a predetermined distance in a row direction on a flat cell array region (A) of the mask ROM, and a plurality of word lines 28 are arranged with a predetermined distance in a column direction to cross with the BN+ diffusion layer 18. And, on a peripheral circuit region (B) of the mask ROM, a BN+ diffusion layer 18 is formed with a bit line contact 50 being in contact with the BN+ diffusion layer. In the drawing, a reference numeral 10 is an active region of silicon substrate and a reference numeral 40 is a code mask region. The BN+ diffusion layer 18 is used as a bit line junction and a source/drain junction of cell transistor. The word line 28 has the same width as the channel width of memory cell.
The mask ROM having the flat cell structure has an isolation layer covering the whole memory cell array region instead of isolation layer such as LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation), to isolate cells in the memory cell array region. The source/drain junction of cell transistor is not isolated since the BN+ diffusion layer 18 is employed, and the contact to the BN+ diffusion layer 18 is disposed on segment selection region (that is, peripheral circuit region), instead of on the memory cell array region. Therefore, the mask ROM of flat cell structure can be advantageously applied to highly-integrated memory having the cell size of 4F2 (F indicates a minimum line width of photolithography) since there is no contact and isolation pattern in the memory cell array region.
FIGS. 2A to 2F are cross-sectional views taken along the line a-a′ in FIG. 1, showing the manufacturing process of a flat cell structure mask ROM in accordance with a conventional method.
Although it is not shown in the drawings, an isolation layer is formed on peripheral circuit region B of silicon substrate 10 by a common isolation process and then, a well is formed by implanting ions into the silicon substrate. The isolation process and the well forming process can be performed in the inverse order.
Referring to FIG. 2A, a sensitive film pattern 16 is formed to have a predetermined size on a flat cell array region A of the silicon substrate 10 and then, BN+ ion implantation process is performed by using the sensitive film pattern 16 as a mask.
Referring to FIG. 2B, the sensitive film pattern is removed and annealing process is performed on the substrate to form a BN+ diffusion layer 18 and a BN oxide layer 20. The BN oxide layer 20 is grown to a predetermined thickness to prevent loss of BN+ diffusion layer 18 junction and to reduce parasitic capacitance between word line and junction.
Referring to FIG. 2C, a gate oxide layer 22 is formed on the flat cell array region A of the silicon substrate 10 and a doped polysilicon layer 24 is formed as a conductive material for gate electrode on the gate oxide layer 22. Then, on the doped polysilicon layer 24, a tungsten silicide layer 26 is formed.
Referring to FIG. 2D, the tungsten silicide layer 26, the doped polysilicon layer 24 and the gate oxide layer 22 are etched to form a word line 28 of flat cell.
Referring to FIG. 2E, an insulation layer is formed on the resulting structure and the layer is subjected to an etch back process to form a spacer 30 on a side wall of the word line 28.
Subsequently, although it is not shown in the drawings, ion implantation process is performed to isolate cells on the flat cell array region A of the resulting substrate. Then, BN+ diffusion layer 24 is formed by performing source/drain ion implantation process on the silicon substrate 10 of peripheral circuit region B, and mask and ion implantation process is performed on the flat cell array region A, thereby coding data.
Referring to FIG. 2F, an interlayer insulating layer 32 is formed on the resulting substrate and then, etched to form a bit line contact (not shown) and a bit line (not shown).
In the memory device of flat cell structure according to the conventional method, a problem has arisen that sheet resistance and contact resistance are increased by high resistance of the BN+ diffusion layer, thereby lowering the speed of the device. Therefore, to solve the problem, a silicide layer is formed on the upper part of the word line. However, it is not formed on the BN+ diffusion layer since there is a possibility of generating shorts between silicide layer and adjacent BN+ diffusion layer.
In a flat cell fabrication process of 0.35 μm technology, it is possible to have compatibility with logic process, however, it is difficult to apply logic process including dual gate and salicide processes for a highly-integrated technology of 0.25 μm or 0.18 μm and below to a flat cell fabrication process. The dual gate process has an advantage of improving P-MOS characteristics using n-type doped polysilicon by employing both n-type doped polysilicon and p-type doped polysilicon as a word line material. The salicide process means a process wherein silicide layers are formed on the active region of the silicon substrate and at the same time, on the word line to reduce electrical resistance of interconnection line.
As a result, it is required to apply dual gate and salicide processes to a flat cell fabrication of 0.25 μm or 0.18 μm and below without forming a silicide layer on the BN+ diffusion layer of the flat cell array region.